In order to make more efficient use of integrated circuit surface area, conventional two-dimensional semiconductor technology has evolved such that contemporary circuits are formed on multiple layers in a three-dimensional configuration. In such configurations, active devices and interconnects are formed in a layered relationship. During the formation of each subsequent layer, an inter-layer pathway, referred to in the art as a xe2x80x9cplugxe2x80x9d, or xe2x80x9cstudxe2x80x9d is electrically coupled between the various active devices and transmission lines of the different layers. To assist in aligning a plug, xe2x80x9clanding padsxe2x80x9d or xe2x80x9ctapsxe2x80x9d are formed in lower layers to serve as a target for the plugs passing from the upper layer. The landing pads are coupled to an underlying circuit or interconnect and are generally larger in surface area than the circuit or interconnect to serve as a wider-tolerance target for the plug.
Such multi-layered technology has enabled the design of highly-integrated memory devices, for example DRAM devices, having extremely high capacity, for example above 1 gigabyte. Such DRAM devices include multiple arrays of memory cells, densely and efficiently laid out under tight design constraints. Between the cell areas are peripheral regions, which include supporting circuitry and interconnect circuitry between the cells, as well as input/peripherals, and the like.
Any misalignment between the vertical plugs and the horizontal interconnect features can cause defects and reliability problems. To ensure that the plug aligns with a feature, the features are made larger than required, for example through the use of landing pads. The area by which the feature is made larger is referred to in the art as a xe2x80x9cborderxe2x80x9d around the vertical contact hole. Any excessive border area thus has a negative impact on circuit density.
Attempts have been made in the past to provide multiple layer interconnect, while reducing or eliminating the border area. These include circuits and fabrication procedures disclosed in U.S. Pat. Nos. 6,083,824, 5,612,254, and 4,966,870.
To a larger extent, the packing density of circuits is limited by how closely the interconnect metal between circuits can be formed without encroaching on each other. These limits are dictated by design rules that govern the separation of one level of contact from another, and by design rules for nesting tolerance or for borders used around contacts.
Other efforts have made toward reducing the high-aspect ratio of the holes made for inter-level interconnects, where the aspect ratio refers the height of a hole as compared to its width. In general, the deeper the hole, the more difficult it is to fabricate the hole. Using the line of an underlying circuit, for example a bit line of a DRAM memory device, as a landing pad, the aspect ratio of the interconnection hole can be significantly reduced.
A typical multiple-layer DRAM memory device 20 is illustrated in FIG. 1. The memory device includes a cell region 22 and a peripheral region 24. The cell region 22 includes active switching devices, coupled to vertically-oriented capacitors 28, that serve as data storage devices. A cell bit line 26 serves as an interconnect to transfer data between peripheral circuit regions and the cell region 22. The peripheral region 24 includes a number of bit lines 32, that function as local interconnects, or studs, electrically coupling between the various active devices and transmission lines of the different layers. An insulative oxide layer 38 is formed above the bit lines 32, and an interconnect stud 34 is opened through the oxide layer and connected to the bit line 32.
When the bit lines 32 are used for local interconnection, for example especially in sense amplifier regions, the layers of circuits can become very dense and crowded. For example, to access the bit line 32 from an upper layer, the region 30 between the bit lines must be accurately etched to form a stud interconnect hole; both in a lateral direction, so as to avoid contact with adjacent bit lines, and in a vertical direction, so as to ensure that the hole is formed at the proper depth. Because the peripheral region 24, for example a sense amplifier region of a DRAM device, is often times densely populated with various interconnect paths, the cross-sectional area of any vertical stud interconnects should be minimized. Therefore, the above case requires subsequent formation of high-aspect-ratio studs that are difficult to achieve using contemporary fabrication processes.
Contemporary techniques of forming the interconnect stud are subject to several process limitations. These include horizontal misalignment, in a lateral direction, where the stud hole may be laterally misaligned with the underlying bit line during formation of the stud hole. Vertical misalignment can also occur, wherein the stud hole is not etched deep enough, so the stud does not make contact with the underlying bit line, or wherein the stud hole is etched too deeply, and is etched through the bit line, as shown in region 36 of FIG. 1.
To improve alignment accuracy, U.S. Pat. No. 5,895,239 discloses a technique for employing a bit line landing pad together with a bit line stud. However, this approach requires tight tolerances at either, or both, the top portions of the bit lines, including the landing pad, and bottom portions of the upper interconnect stud, so as to provide a minimal width at the top of the bit line, and a maximum width at the bottom of the upper interconnect stud. A wide stud top limits circuit density considerations, while a narrow stud bottom leads to increased contact resistance and an increased aspect ratio that is difficult to accurately fabricate. No provision is made for vertical alignment of the stud, so if the stud hole is slightly misaligned with the underlying bit line, a void can be formed in the underlying inter-layer dielectric adjacent the stud.
Another approach at multiple-layered interconnect is disclosed in U.S. Pat. No. 5,891,799. In this approach, an etch-stop layer, for example a silicon nitride masking layer (Si3N4) is formed over an inter-layer dielectric (SiO2). Stud holes are patterned in the mask layer and underlying dielectric layer for the deposit of studs to connect to the lower layer. Once the studs are formed, the masking layer later serves as an etching reference for eventual formation of landing pads for studs formed through an upper layer. However, this technique suffers from a number of limitations. Since the Si3N4 masking layer is a high-stress-bearing material, and is formed indiscriminately as a layer over the entire circuit, this configuration imparts undue stress on the various layers, which may lead to warping of the circuit. Additionally, due to its high density, the masking layer prevents outgassing of impurities contained in the inter-layer dielectric, for example C, F, and Cl, during later high-temperature processes. The remaining Si3N4 masking layer would prevent the introduction of H2 and O2 during popular alloy processes, greatly affecting the conductive adhesiveness between the upper and lower metals and defect curing efficiency.
Furthermore, this process is incompatible with contemporary memory fabrication processes, because the Si3N4 masking layer would be applied between bit lines. With reference again to FIG. 1, dielectric spacers 40A, 40B are formed on each lateral side of cell bit line 26A prevent shorting between the cell bit line 26A and the capacitor 28. In order to make such spacers 40A, it would be necessary to remove any masking layer between adjacent bit lines 26A, 26B to allow for space for the capacitors 28 to be inserted between the bit lines 26A, 26B. However, this process would also remove any dielectric layer 42A, 42B formed over the bit lines 26A, 26B necessary for insulating the bit lines 26A, 26B from the capacitors. This would also remove any masking layer on either side of the peripheral region bit lines 32, defeating the purpose of forming the masking layer in the first place.
The present invention is directed to a fabrication process and circuit that addresses the limitations of conventional techniques. For example, the present invention provides an etch-stop layer that is selectively patterned on only a portion of the underlying inter-layer dielectric, thereby allowing for outgassing during later fabrication processes. Additionally, the etch stop layer may be formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer.
In one aspect, the present invention is directed to a semiconductor device comprising a first insulating layer and a first stud formed in the first insulating layer. An etch stop material layer is formed over the first stud and a second insulating layer is formed over the etch stop material layer. A second connectivity stud is formed through the second insulating layer and through the etch stop material layer, the first and second studs being in electrical contact with each other.
In a preferred embodiment, the etch stop material layer and second insulating layer have different etching selectivities. The second connectivity stud may formed by first etching the second insulating layer to the etch stop layer, followed by etching the etch stop material layer to expose the first stud. The etch stop material layer preferably may comprise silicon nitride. An etch-blocking layer may be provided above the first stud and below the etch-stop material layer.
In another aspect, the present invention is directed to a semiconductor device comprising first and second circuit regions laterally disposed in a first insulating layer, wherein the first circuit region comprises a conductive line, and wherein the second circuit region comprises a stud. An etch stop material layer is formed over the conductive line and the stud, the etch stop layer being selectively patterned in the first circuit region to form lateral spacers on lateral faces of the conductive line, the etch stop layer coating the second circuit region. A second insulating layer is formed over the etch stop layer, and a contact hole is provided through the second insulating layer, and through the etch stop layer to expose an upper portion of the stud. Contact metal is provided in the contact hole, electrically contacting the stud.
The first circuit region preferably comprises a cell region and the second circuit region preferably comprises a peripheral region of a memory device. The conductive line may comprise a bit line of the memory device.
The etch stop material layer may comprise silicon nitride. The etch stop material layer and second insulating layer may have different etching selectivities. The contact hole may be formed by first etching the second insulating layer to the etch stop material layer, followed by etching the etch stop material layer to expose the stud. The etch stop material layer may forms lateral spacers for the conductive lines in the first circuit region. An etch-blocking layer may be formed above the stud and below the etch-stop material layer.
In another aspect the present invention is directed to a semiconductor device comprising a circuit formed in a semiconductor substrate, the circuit having first and second terminals. A first insulating layer is formed above the circuit and a stud hole is formed in the first insulating layer above the first terminal. An electrically conductive stud is formed in the stud hole, electrically contacting the first terminal. A conductive line is formed on the first insulating layer above the second terminal, the conductive line electrically contacting the second terminal. An etch stop material layer is formed over the first insulating layer, stud, and conductive line, the etch stop material layer providing insulative spacers on lateral portions of the conductive line. A second insulating layer is formed over the etch stop material layer, and contact hole is formed through the second insulating layer, and through the etch stop layer to an upper portion of the stud. Contact metal is formed in the contact hole, electrically contacting the stud.
In another aspect, the present invention is directed to a semiconductor device comprising first and second circuit regions laterally disposed in a first insulating layer, wherein the first circuit region comprises a conductive line, and wherein the second circuit region comprises a stud. An etch stop material layer is formed over the conductive line and the stud, the etch stop layer being selectively patterned in the first circuit region to form lateral spacers on lateral faces of the conductive line, the etch stop layer coating the second circuit region. A second insulating layer is formed over the etch stop layer and a contact hole is provided through the second insulating layer, and through the etch stop layer, to expose an upper portion of the stud. Contact metal is provided in the contact hole, electrically contacting the stud, such that the etch stop material layer operates to form lateral insulative spacers of the conductive line and serves as an etch stop during forming of the contact hole.
In another aspect, the present invention is directed to a method for forming a semiconductor device. A first insulating layer is formed above a semiconductor circuit. A first stud hole is provided in the first insulating layer, and conductive material is deposited to form a first stud in the first stud hole. An etch stop material layer is provided over the first stud and a second insulating layer is provided over the etch stop material layer. A second stud hole is provided through the second insulating layer and through the etch stop material layer to expose a top portion the first stud. Conductive material is provided to form a second stud in the second stud hole.
In a preferred embodiment, the second stud hole is formed by first etching the second insulating layer to the etch stop material layer, followed by second etching the etch stop material layer to expose the first stud. The first etching may be performed with an oxide etchant gas, and the second etching may be performed using a nitride etchant gas.
In another aspect, the present invention is directed to a method for forming a semiconductor device. A first insulating layer is formed above a semiconductor circuit. A first circuit region comprising a conductive line is formed on the first insulating layer, and a second circuit region comprising a stud is formed through the first insulating layer. An etch stop material layer is formed over the first and second regions. Lateral spacers are formed in the first circuit region on lateral faces of the conductive line by selectively removing the etch stop material layer in the first circuit region while leaving the etch stop material layer substantially intact in the second circuit region. A second insulating layer is formed over the first and second circuit regions, and a contact hole is provided through the second insulating layer, and through the etch stop layer to expose an upper portion of the stud. Contact metal is provided in the contact hole, electrically contacting the stud.
In another aspect, the present invention is directed to a method for forming a semiconductor device. A circuit having first and second terminals is formed in a semiconductor substrate. A first insulating layer is formed above the circuit, and a stud hole is etched above the first terminal. Electrically conductive contact metal is formed in the stud hole, electrically contacting the first terminal. A conductive line is formed on the insulating layer above the second terminal, the conductive line electrically contacting the second terminal. An etch stop material layer is provided over the first insulating layer, stud, and conductive line. The etch stop material layer is selectively removed to provide insulative spacers on lateral portions of the conductive line, and to substantially retain the etch stop material layer in a region above the stud. A second insulating layer is formed over the etch stop material layer. A contact hole is provided through the second insulating layer, and through the etch stop layer to an upper portion of the stud. electrically conductive contact metal is provided in the contact hole.